Samsung renames next DRAM node around wafer bonding, ZDNet Korea says

Samsung Electronics has moved B1b, a wafer-to-wafer hybrid bonding process, onto its official DRAM roadmap and given it the D0a designation, ZDNet Korea reported on Wednesday. B1b had been in research and development outside the roadmap until the revision.

Two accounts carried the reporting. jukan05 posted a full translation of the article, and SemiconductorsX summarised it and quoted the same unnamed source. Both trace to ZDNet Korea, which attributes the change to people close to the plan. Samsung has not published anything on the revision.

D0a is meant to be Samsung's first DRAM below 10 nanometres. The most recent part in volume is 1c, around 11 to 12 nanometres, with 1d at 10 to 11 and likely the last of the class, according to the report, which notes these are marketing terms rather than physical dimensions.

B1b builds the memory cells on one wafer and the driver circuitry on another, then joins them by connecting their copper interconnects directly. Vertical-channel DRAM, now labelled D0a-V, takes a different route, cutting cell area from 6F² to 4F², but it needs high-aspect-ratio etching and new materials to hold down leakage.

Samsung is reviewing B1b for HBM5, which the report expects in mass production around 2029 with a target of 50% or more over HBM4E on operating speed. Commercialisation of B1b-based D0a is at least two years out, and the industry expects the investment schedule around the middle of next year, the report said.